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Home > News > GOTiT e-seminar with HLST contribution on February 22th at 13:00 CET

GOTiT e-seminar with HLST contribution on February 22th at 13:00 CET

The title of the talk will be "Performance Tuning Using Vectorization" given by Nicolay J. Hammer.

The talk will provide practical guidelines for software developers on the
HPC-FF computer at JSC which are tackling the single processor performance
of their code using vectorization. It is a compendium of a study about the
performance improvement potentials due to the vectorization of specific
intrinsic functions on Intel's Nehalem architecture. A comparison with the
vectorization capabilities of IBM's POWER6 architecture will be presented.

In this study we focus on Single Instruction, Multiple Data (SIMD)
architectures, where one single instruction is executed on a multiple set
of data in parallel. The double precision (64 bit) test cases under
consideration are guided by the conditions in realistic numerical
simulation codes.