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First European training session for Intel MIC users at IFERC-CSC

Since MIC processors differ significantly from conventional (Xeon) processors, users sending an expression of interest should have some experience of programming MIC processors or should attend one training session organized by the CSC.

Registration for the first European training session, which will take place on February 26-27, is handled by IPP in Garching (Germany). If you are interested in participating in this training course, please contact Ms. Anneliese Grasmann anneliese.grasmann@ipp.mpg.de with copy to Jacques David jacques.david@iferc.org and Roman Hatzky roman.hatzky@ipp.mpg.de no later than Wednesday 19th February 2014.