Abstract of MICPORT Project

Since many years Moore's law is not driven any more by increasing clock speed but by an exponential growth of number of cores. This trend is especially pronounced by so-called accelerator cards which are offered by two large vendors: NVIDIA (GPU) and Intel (Xeon Phi). It is very likely that future HPC hardware will be dominated by such platforms which are either GPU like systems or independent many integrated core (MIC) architectures with dozens of cores and hundreds to thousands of threads. Such systems show a very high peak performance combined with high energy efficiency so that many computing facilities, including IFERC-CSC, are already planning to extend their compute resources by purchasing some of these accelerator cards. Therefore, it is of key importance to keep track of such developments of future HPC architectures. It is planned to port the JOREK code to the Intel MIC architecture to gain experience with the new hardware and software stack. The corresponding Intel MIC hardware will be provided by Rechenzentrum Garching (RZG) which is another collaborator of this project.